1. Field of the Invention
The present invention relates to a semiconductor device having a polycide wiring structure, and also to a manufacturing method of the same.
2. Description of the Related Art
A so-called polycide wiring structure is applied to many of the recent semiconductor devices since the structure is suited to high integration. In this polycide wiring structure, a polysilicon layer, which is the same layer as the gate electrode of a memory cell of a DRAM or a logic element, is extended continuously and used as a wiring layer. Compared to a metal wiring structure (wherein an allowance has to be provided between a contact and a gate, between different contacts, and between a contact and a metal layer), the polycide wiring structure is suitably applied to high integration of semiconductor devices since the wiring layer is the same polysilicon layer as the gate electrode and therefore enables small layout patterns. In many cases, the polycide wiring structure is a multi-layered structure wherein a polysilicon layer is overlaid with a silicide layer (refer to Jpn. Pat. Appln. KOKAI Publication No. 2003-100748, for example).
The polycide wiring structure is not advantageously applied to devices requiring high-speed operations, because the polysilicon layer it uses has a higher resistance than that of a metal wiring layer (which is formed of Al or Cu) and therefore causes an increase in the RC delay.
If a thick silicide layer is formed on the polysilicon, the resistance will decrease and a high-speed operation can be expected. However, the thickness of the silicide layer cannot be controlled with high precision when the layer is formed. If the silicide layer is too thick, it may react with the gate insulating film and penetrate the gate insulating film, causing short circuits.